From 4fc2f8b56345eb00d7f6bfc4c98b4e5d0cea8bf0 Mon Sep 17 00:00:00 2001 From: Tiago Batista Cardoso Date: Sun, 21 Dec 2025 11:07:04 +0100 Subject: [PATCH] first --- count.vhdl | 32 +++++++++++++++++++ tb_traffic_light.fst | Bin 0 -> 3809 bytes tb_traffic_light.vhdl | 50 ++++++++++++++++++++++++++++++ tick1ms.vhdl | 50 ++++++++++++++++++++++++++++++ tick1s.vhdl | 70 ++++++++++++++++++++++++++++++++++++++++++ traffic_light.vhdl | 26 ++++++++++++++++ 6 files changed, 228 insertions(+) create mode 100644 count.vhdl create mode 100644 tb_traffic_light.fst create mode 100644 tb_traffic_light.vhdl create mode 100644 tick1ms.vhdl create mode 100644 tick1s.vhdl create mode 100644 traffic_light.vhdl diff --git a/count.vhdl b/count.vhdl new file mode 100644 index 0000000..96feaed --- /dev/null +++ b/count.vhdl @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity count is + port ( + rst, + clk : in std_logic; + in_s: in std_logic_vector (31 downto 0); + out_s : out std_logic_vector (31 downto 0) + ); +end entity count; + +architecture V1 of count is +begin + -- l'utilisation d'entiers 32 bits nous limite a une valeur maximale de 2,147,483,647. + -- dans le cas d'un overflow, la valeur se reinitialise a 0. + assert in_s /= x"FFFFFFFF" report "counter overflow. wrapping value to 0" severity WARNING; + + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + out_s <= (others => '0'); + else + out_s <= to_std_logic_vector(unsigned(in_s) + 1); + end if; + end if; + end process; + +end architecture V1; diff --git a/tb_traffic_light.fst b/tb_traffic_light.fst new file mode 100644 index 0000000000000000000000000000000000000000..ea94175a5cbb38ff9db3f1ecd8e0be5389b88286 GIT binary patch literal 3809 zcmdUu_dgVX|Hs=&Rz^DFvhL8?JF65jPnlVlO=g*gPC~hJCuc`SWRI*ndt{yH>?nJm zGY@gX<@^2CFQ4z9@Ol06dcEI|=daH{Xa0t1?q5^;fiZOd=K0Nx5F_Kj2|~o`0)0|O z@E3Y6>(UqRUZV;xuwX4qvtP}pxegU;UWj-NhJ3U#|C!8T^5TiRphlBVQ4W7fp^kOY zL}oRLMcmTTqL-I1|9Y8@ly*XsFg~oaWjknw+_H__JK6nC(pMV@B{;5hJU@fg3PE_7 zp});LC|5L#FG+h|b+?~a{GJ-;0>#iS4tF=DCcyOHa*nLb<2Ovk>sx#|kB*vy)=m#0 zB(LW-_~(ZMa|$0ceL2NMmKVH3JP<8GJ0S8j0p7U%u%B&}refx)!w0K1+)x4NsZ+5#h?a6)(PyqL{QPC6 z52v&zq@8>7fmy>FT0j-~ry=j*(_x1aytT%jZi{2vWMcDgQ~W@!n$1tUeX7EdUl&25 zM{#qiLXIj1sYk%dYe-}J=@;);rwn>e{HXshxmoAvJl9r+17EdF+uC2_rD$DFg2Eo1 zz#qhH*v5FhBC+_{2RrT*t&6>+@~-jjX#qB0_v+3fk3s|VzBa3~bv*7?F_=bgR+1ubXx^3nxvq_=q-ev#U}S65X6~X$ z;xr$C<7`>~1l3RVh)pFdswu=x%jv#*yu6M1fK{ncDt*KK%eP-xa=IJ)6~ND;Vy5jP zlJ1w)PpD+XbCw!O-CyO1Een{Cv;pu5tt`n&rwrdF5@M_bYKj`FJKLM|z8Se`nyhxu4|FR)$o1e{-Zl#DbD31I}VSkBv36n?XSJvtj)Q zW1HNq(L3u0*Q$4)CC#gv0@f~V+D~6=SNMDnFl4M+$U8hi4q%f(yXecEIDIko^REoR zmq$`0Gf5K6mH#pyW128{*JMI}UCF)Fuw=+Y_^n{zwCV&I*TDYfu2F1F!ZJ27ai z2GS~OA@*I`&%V9S!o@NZR`!_cN^Y>X$5)O;&Nk?E>;Xp%F0R<#7*p(YR+()Jw=2v2 zG3A1|$q-=~fvDGWYRU56l6E1f&;R&kkWpLUy(F&-Y{A&_v|!5H*5nb@xDtem=R`(u zSGUO~G6rZ*4lKu^h8qz*SZOaFXP4@%OECDa>DG6}{ZSa$?&o(N^~}A7WiJvrY82dp z_Z_Zi&s1ecjIg2l1SXu)uG83ObR8m}2gJDsKd#&e4#`^ih>-Pm8w?)~BH-i0IgS`r zyaqFeNP>B2XRPy0 z-!dtfjC?xH&bP+bb%MmPizMp@7#0*#F2q^%rd+3dfk~w!C zv*&pjb`QOhcOk0LAhzfQqrfU9zTDD}VmiLMt*=r(DGn2PRnkWA7QPR*`y51=0t*gua^nJgSG9R2H)I?4WujM`T4fT*PFMi~5k1poaYuLgBW?)BM=a!l)0HzWZS2oCwWiT0?tFNm)mTrQ5*>Sbq|@05 z*Kp$3HXHHUlC1T6R&%5fy$l!Xjm+FdA6zm>L2y-yLQD16u#9+Sx6D;fq|qV*(e$3f z+R$5K%z7MpYxnJT@@@1vgnfnn#7rr9e3EUxJL2SmsZv3+)<{txXhsHgs3ZCWdYtY2 z&|5naz?{0U*B3FFm*(8ecFm1Fjdjnd_<)y~J%f#wOipF+k-+WllmN5sEQp8SnU^L1 z%o3`P3yZ#l&i+b39UK5PW>!Pie;2feoo*zMUHEywsT<+Fn_ae2#!uEp>=zdl^)$@2 z%a!+NI_WkW+sXmZ{Fe=?P0NE3K3cTVa*zGZU{d+UX!+5vnDvatwQZOvpvh*E5BW^r zJ>aLEf=x<@lB}efkNI3x8)JB7xbnGo4Ig}p0+lv%{6u__5-16jn69{`aiT>HKH8?H zLHMI^xp1CvzHm{rY3CD;X3-hJ1e1qcLIgpQP?ny!POlJ2&@}#PJX?J5S2yJ2#~`KK zMTtE^1R?);W7en#prRxbJ#k$_T`oa6R@2>~g7l?z2DvF|FA3_I+NhA^;Mhm(2v}u)=HP`zzsw=ct z1-|j(2=qf55LQg5Bzs4bkwht1S@-autbWWhDVI@zGMcwLeo(OV>Sp`(+?dLkRZR#d zu`4qhDyclmbo(xmU;BAwwuK1->zFSAr%7B29%-AyG0X{+!K+# zI9>b;ob)|Ff&Qaz;e$0{ z_7Oz3su1rI-r`STbICrrs+w%mr`OMXYMV8)Z#Ro0T5$?gM^Hy#Cl$?K6!$Q0+}*G$ zp3_l6e@8!|zc2RDob8+^n2zlYGW~)<4#+Oyhrt}^1zQ8s>D>E=phTqc#iAS&yW%?N zAb5@K012i8MT6+T(Rvqza#-z6>`NK3ee3ysb zM7Ol5IuT3y+Obr$djp=V@;DO&jVJXAETu0&;IS&YnS7+4JuHhO4=cuzfBRNCHpr2) zis9$0PJZRMq#iRtz;CuHb~x}!gby|l%Zz;x`4*zBc6W^bXOE~Oce~c%L*XjkCm0WH zvs+ei7cSgu$6_AdtYU*R>u5iYQxRm)(X@|)2(s$jkB_q!JohuQBJQRj{nxvS4_o*; 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+ wait for 2500 ns; + rst_s <= '0'; + wait for clk_period; + + wait for clk_period; + + while true loop + wait until rising_edge(clk_s); + end loop; + end process stim_proc; +end architecture sim; diff --git a/tick1ms.vhdl b/tick1ms.vhdl new file mode 100644 index 0000000..97c0fc5 --- /dev/null +++ b/tick1ms.vhdl @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; + +-- utilise un counter pour envoyer un signal toutes les milisecondes +-- la frequence de rafraichissement de notre programme (clock rate) est de 10ns (100MHz) +-- il faut alors envoyer un signal toutes les 100,000 (x"186A0") tours d'horloge. +entity tick1ms is + port ( + rst, + clk : in std_logic; + output : out std_logic + ); +end entity tick1ms; +architecture V1 of tick1ms is + component count is + port( + rst, + clk : in std_logic; + input : in std_logic_vector (31 downto 0); + output : out std_logic_vector (31 downto 0) + ); + end component; + -- instanciation du signal in_s a 0. + signal counter_in : std_logic_vector (31 downto 0) := (others => '0'); + signal counter_out : std_logic_vector (31 downto 0); +begin + G1: entity work.count(V1) + port map( + rst => rst, + clk => clk, + in_s => counter_in, + out_s => counter_out + ); + + process(clk, rst) + begin + if rising_edge(clk) then + if rst = '1' then + output <= '0'; + elsif counter_out = x"000001f4" then -- 1ms se sont ecoulees + output <= '1'; + counter_in <= (others => '0'); + else + output <= '0'; + counter_in <= counter_out; + end if; + end if; + end process; + +end architecture V1; diff --git a/tick1s.vhdl b/tick1s.vhdl new file mode 100644 index 0000000..4f16079 --- /dev/null +++ b/tick1s.vhdl @@ -0,0 +1,70 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tick1s is + port ( + rst, + clk : in std_logic; + output : out std_logic + ); +end entity tick1s; +architecture V1 of tick1s is + component count is + port( + rst, + clk : in std_logic; + input : in std_logic_vector (31 downto 0); + output : out std_logic_vector (31 downto 0) + ); + end component; + component tick1ms is + port ( + rst, + clk : in std_logic; + output : out std_logic + ); + end component; + signal counter_in : std_logic_vector (31 downto 0) := (others => '0'); + signal counter_out : std_logic_vector (31 downto 0); + signal ms_s : std_logic; +begin + G1: entity work.tick1ms(V1) + port map( + rst => rst, + clk => clk, + output => ms_s + ); + G2: entity work.count(V1) + port map( + rst => rst, + clk => ms_s, + in_s => counter_in, + out_s => counter_out + ); + + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + output <= '0'; + elsif counter_out = x"000003e8" then + output <= '1'; + counter_in <= (others => '0'); + else + output <= '0'; + if ms_s = '1' then + counter_in <= counter_out; + end if; + end if; + + -- if output = '1' then + -- else + -- if ms_s = '1' then + -- counter_in <= counter_out; + -- end if; + -- end if; + end if; + end process; + + +end architecture V1; diff --git a/traffic_light.vhdl b/traffic_light.vhdl new file mode 100644 index 0000000..1f6c816 --- /dev/null +++ b/traffic_light.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_arith.all; +use ieee.std_logic_1164.all; + +entity traffic_light is + port ( + rst, + clk : in std_logic; + red, + orange, + green : out std_logic + ); +end entity traffic_light; + +architecture V1 of traffic_light is + component tick1s is + port ( + rst, + clk : in std_logic; + output : out std_logic + ); + end component; +begin + + +end architecture V1;