diff --git a/tb_traffic_light.vhdl b/tb_traffic_light.vhdl
index afa8202..19fae4a 100644
--- a/tb_traffic_light.vhdl
+++ b/tb_traffic_light.vhdl
@@ -15,7 +15,7 @@ architecture sim of tb_traffic_light is
 
     constant clk_period : time := 1000 ns;
 begin
-    -- Instantiate DUT
+    -- instanciation de l'uut
     UUT: entity work.traffic_light
         port map (
             rst    => rst_s,
@@ -25,7 +25,7 @@ begin
             red => red_s
         );
 
-    -- Clock generator
+    -- horloge
     clk_proc: process
     begin
         while true loop
@@ -36,7 +36,7 @@ begin
         end loop;
     end process;
 
-    -- Stimulus
+    -- processus
     stim_proc: process
     begin
         -- apply reset
diff --git a/tick1s.vhdl b/tick1s.vhdl
index 697d945..d34f385 100644
--- a/tick1s.vhdl
+++ b/tick1s.vhdl
@@ -48,7 +48,8 @@ begin
         if rising_edge(clk) then
             if rst = '1' then
                 output <= '0';
-            elsif counter_out = x"000003e8" then
+            --elsif counter_out = x"000003e8" then (Valeur pour une vraie seconde)
+            elsif counter_out = x"0000000A" then -- Valeur utilisee pour tester sans simuler un nombre trop consequent de tour d'horloges
                 output <= '1';
                 counter_in <= (others => '0');
             else
diff --git a/traffic_light.vhdl b/traffic_light.vhdl
index b54411c..24aa193 100644
--- a/traffic_light.vhdl
+++ b/traffic_light.vhdl
@@ -11,7 +11,6 @@ entity traffic_light is
         green : out std_logic
     );
 end entity traffic_light;
-
 architecture V1 of traffic_light is
     component count is
     port(
@@ -28,11 +27,11 @@ architecture V1 of traffic_light is
         output : out std_logic
     );
     end component;
-    signal s_clk : std_logic;
     signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
     signal counter_out : std_logic_vector (31 downto 0);
+    signal s_clk : std_logic;
 begin
-    G1: entity work.tick1ms(V1)
+    G1: entity work.tick1s(V1)
     port map(
         rst => rst,
         clk => clk,
@@ -54,27 +53,28 @@ begin
                 green <= '1';
                 orange <= '0';
                 red <= '0';
-                s_clk <= '0';
-                counter_in <= x"00000000";
             else
-                if counter_out < x"0000000a" then
+                -- 10 seconds green light
+                if counter_out < x"0000000a" then 
                     green <= '1';
                     orange <= '0';
                     red <= '0';
-                    if s_clk = '1' then
-                        counter_in <= counter_out;
-                    end if;
-                elsif counter_out < x"00000014" then
+                -- 2 seconds orange light
+                elsif counter_out < x"0000000c" then
                     green <= '0';
                     orange <= '1';
                     red <= '0';
-                    if s_clk = '1' then
-                        counter_in <= counter_out;
-                    end if;
-                else
-                    if s_clk = '1' then
-                        counter_in <= counter_out;
-                    end if;
+                -- 10 seconds red light
+                elsif counter_out < x"00000016" then
+                    green <= '0';
+                    orange <= '0';
+                    red <= '1';
+                -- reset
+                else 
+                    counter_in <= (others => '0');
+                end if;
+                if s_clk = '1' then
+                    counter_in <= counter_out;
                 end if;
             end if;
         end if;