[wip] traffic_light state machine

tb_traffic_light.vhdl

@@ -9,16 +9,20 @@ end entity;
 architecture sim of tb_traffic_light is
     signal rst_s   : std_logic := '1';
     signal clk_s   : std_logic := '0';
-    signal out_s   : std_logic;
+    signal green_s   : std_logic;
+    signal orange_s   : std_logic;
+    signal red_s   : std_logic;
 
     constant clk_period : time := 1000 ns;
 begin
     -- Instantiate DUT
-    UUT: entity work.tick1s
+    UUT: entity work.traffic_light
         port map (
             rst    => rst_s,
             clk    => clk_s,
-            output => out_s
+            green => green_s,
+            orange => orange_s,
+            red => red_s
         );
 
     -- Clock generator