[wip] traffic_light state machine

tick1s.vhdl

@@ -26,18 +26,19 @@ architecture V1 of tick1s is
     end component;
     signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
     signal counter_out : std_logic_vector (31 downto 0);
-    signal ms_s : std_logic;
+    signal ms_clk : std_logic;
 begin
     G1: entity work.tick1ms(V1)
     port map(
         rst => rst,
         clk => clk,
-        output => ms_s
+        output => ms_clk
     );
     G2: entity work.count(V1)
     port map(
         rst => rst,
-        clk => ms_s,
+        -- on utilise le signal de sortie du tick1ms comme clock pour notre counter.
+        clk => ms_clk,
         in_s => counter_in,
         out_s => counter_out
     );
@@ -52,17 +53,10 @@ begin
                 counter_in <= (others => '0');
             else
                 output <= '0';
-                if ms_s = '1' then
+                if ms_clk = '1' then
                     counter_in <= counter_out;
                 end if;
             end if;
-
-               -- if output = '1' then
-               -- else
-               --     if ms_s = '1' then
-               --         counter_in <= counter_out;
-               --     end if;
-               -- end if;
         end if;
     end process;