[wip] traffic_light state machine

tb_traffic_light.vhdl

@@ -9,16 +9,20 @@ end entity;
 architecture sim of tb_traffic_light is
     signal rst_s   : std_logic := '1';
     signal clk_s   : std_logic := '0';
-    signal out_s   : std_logic;
+    signal green_s   : std_logic;
+    signal orange_s   : std_logic;
+    signal red_s   : std_logic;
 
     constant clk_period : time := 1000 ns;
 begin
     -- Instantiate DUT
-    UUT: entity work.tick1s
+    UUT: entity work.traffic_light
         port map (
             rst    => rst_s,
             clk    => clk_s,
-            output => out_s
+            green => green_s,
+            orange => orange_s,
+            red => red_s
         );
 
     -- Clock generator

tick1s.vhdl

@@ -26,18 +26,19 @@ architecture V1 of tick1s is
     end component;
     signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
     signal counter_out : std_logic_vector (31 downto 0);
-    signal ms_s : std_logic;
+    signal ms_clk : std_logic;
 begin
     G1: entity work.tick1ms(V1)
     port map(
         rst => rst,
         clk => clk,
-        output => ms_s
+        output => ms_clk
     );
     G2: entity work.count(V1)
     port map(
         rst => rst,
-        clk => ms_s,
+        -- on utilise le signal de sortie du tick1ms comme clock pour notre counter.
+        clk => ms_clk,
         in_s => counter_in,
         out_s => counter_out
     );
@@ -52,17 +53,10 @@ begin
                 counter_in <= (others => '0');
             else
                 output <= '0';
-                if ms_s = '1' then
+                if ms_clk = '1' then
                     counter_in <= counter_out;
                 end if;
             end if;
-
-               -- if output = '1' then
-               -- else
-               --     if ms_s = '1' then
-               --         counter_in <= counter_out;
-               --     end if;
-               -- end if;
         end if;
     end process;
     

traffic_light.vhdl

@@ -13,6 +13,14 @@ entity traffic_light is
 end entity traffic_light;
 
 architecture V1 of traffic_light is
+    component count is
+    port(
+        rst,
+        clk : in std_logic;
+        input : in std_logic_vector (31 downto 0);
+        output : out std_logic_vector (31 downto 0)
+    );
+    end component;
     component tick1s is 
     port (
         rst,
@@ -20,7 +28,56 @@ architecture V1 of traffic_light is
         output : out std_logic
     );
     end component;
+    signal s_clk : std_logic;
+    signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
+    signal counter_out : std_logic_vector (31 downto 0);
 begin
-    
+    G1: entity work.tick1ms(V1)
+    port map(
+        rst => rst,
+        clk => clk,
+        output => s_clk
+    );
+    G2: entity work.count(V1)
+    port map(
+        rst => rst,
+        -- on utilise le signal de sortie du tick1s comme clock pour notre counter.
+        clk => s_clk,
+        in_s => counter_in,
+        out_s => counter_out
+    );
+
+    process(clk, rst) -- state machine
+    begin
+        if rising_edge(clk) then
+            if rst = '1' then
+                green <= '1';
+                orange <= '0';
+                red <= '0';
+                s_clk <= '0';
+                counter_in <= x"00000000";
+            else
+                if counter_out < x"0000000a" then
+                    green <= '1';
+                    orange <= '0';
+                    red <= '0';
+                    if s_clk = '1' then
+                        counter_in <= counter_out;
+                    end if;
+                elsif counter_out < x"00000014" then
+                    green <= '0';
+                    orange <= '1';
+                    red <= '0';
+                    if s_clk = '1' then
+                        counter_in <= counter_out;
+                    end if;
+                else
+                    if s_clk = '1' then
+                        counter_in <= counter_out;
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
     
 end architecture V1;