library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tb_traffic_light is
end entity;

architecture sim of tb_traffic_light is
    signal rst_s   : std_logic := '1';
    signal clk_s   : std_logic := '0';
    signal out_s   : std_logic;

    constant clk_period : time := 1000 ns;
begin
    -- Instantiate DUT
    UUT: entity work.tick1s
        port map (
            rst    => rst_s,
            clk    => clk_s,
            output => out_s
        );

    -- Clock generator
    clk_proc: process
    begin
        while true loop
            clk_s <= '0';
            wait for clk_period/2;
            clk_s <= '1';
            wait for clk_period/2;
        end loop;
    end process;

    -- Stimulus
    stim_proc: process
    begin
        -- apply reset
        rst_s <= '1';
        wait for 2500 ns;
        rst_s <= '0';
        wait for clk_period;

        wait for clk_period;

        while true loop
            wait until rising_edge(clk_s);
        end loop;
    end process stim_proc;
end architecture sim;