library ieee;
use ieee.std_logic_1164.all;

entity tick1s is
    port (
        rst,
        clk : in std_logic;
        output : out std_logic
    );
end entity tick1s;
architecture V1 of tick1s is
    component count is
    port(
        rst,
        clk : in std_logic;
        input : in std_logic_vector (31 downto 0);
        output : out std_logic_vector (31 downto 0)
    );
    end component;
    component tick1ms is
    port (
        rst,
        clk : in std_logic;
        output : out std_logic
    );
    end component;
    signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
    signal counter_out : std_logic_vector (31 downto 0);
    signal ms_s : std_logic;
begin
    G1: entity work.tick1ms(V1)
    port map(
        rst => rst,
        clk => clk,
        output => ms_s
    );
    G2: entity work.count(V1)
    port map(
        rst => rst,
        clk => ms_s,
        in_s => counter_in,
        out_s => counter_out
    );

    process(clk)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                output <= '0';
            elsif counter_out = x"000003e8" then
                output <= '1';
                counter_in <= (others => '0');
            else
                output <= '0';
                if ms_s = '1' then
                    counter_in <= counter_out;
                end if;
            end if;

               -- if output = '1' then
               -- else
               --     if ms_s = '1' then
               --         counter_in <= counter_out;
               --     end if;
               -- end if;
        end if;
    end process;
    
    
end architecture V1;