library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;

entity traffic_light is
    port (
        rst,
        clk : in std_logic;
        red,
        orange,
        green : out std_logic
    );
end entity traffic_light;

architecture V1 of traffic_light is
    component tick1s is 
    port (
        rst,
        clk : in std_logic;
        output : out std_logic
    );
    end component;
begin
    
    
end architecture V1;