library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;

entity traffic_light is
    port (
        rst,
        clk : in std_logic;
        red,
        orange,
        green : out std_logic
    );
end entity traffic_light;
architecture V1 of traffic_light is
    component count is
    port(
        rst,
        clk : in std_logic;
        input : in std_logic_vector (31 downto 0);
        output : out std_logic_vector (31 downto 0)
    );
    end component;
    component tick1s is 
    port (
        rst,
        clk : in std_logic;
        output : out std_logic
    );
    end component;
    signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
    signal counter_out : std_logic_vector (31 downto 0);
    signal s_clk : std_logic;
begin
    G1: entity work.tick1s(V1)
    port map(
        rst => rst,
        clk => clk,
        output => s_clk
    );
    G2: entity work.count(V1)
    port map(
        rst => rst,
        -- on utilise le signal de sortie du tick1s comme clock pour notre counter.
        clk => s_clk,
        in_s => counter_in,
        out_s => counter_out
    );

    process(clk, rst) -- state machine
    begin
        if rising_edge(clk) then
            if rst = '1' then
                green <= '1';
                orange <= '0';
                red <= '0';
            else
                -- 10 seconds green light
                if counter_out < x"0000000a" then 
                    green <= '1';
                    orange <= '0';
                    red <= '0';
                -- 2 seconds orange light
                elsif counter_out < x"0000000c" then
                    green <= '0';
                    orange <= '1';
                    red <= '0';
                -- 10 seconds red light
                elsif counter_out < x"00000016" then
                    green <= '0';
                    orange <= '0';
                    red <= '1';
                -- reset
                else 
                    counter_in <= (others => '0');
                end if;
                if s_clk = '1' then
                    counter_in <= counter_out;
                end if;
            end if;
        end if;
    end process;
    
end architecture V1;