library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity count is
    port (
        rst,
        clk : in std_logic;
        in_s: in std_logic_vector (31 downto 0);
        out_s : out std_logic_vector (31 downto 0)
    );
end entity count;

architecture V1 of count is
begin
    -- l'utilisation d'entiers 32 bits nous limite a une valeur maximale de 2,147,483,647.
    -- dans le cas d'un overflow, la valeur se reinitialise a 0.
    assert in_s /= x"FFFFFFFF" report "counter overflow. wrapping value to 0" severity WARNING;

    process(clk)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                out_s <= (others => '0'); 
            else
                out_s <= to_std_logic_vector(unsigned(in_s) + 1);
            end if;
        end if;
    end process;

end architecture V1;