27 lines
450 B
VHDL
27 lines
450 B
VHDL
library ieee;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_1164.all;
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entity traffic_light is
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port (
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rst,
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clk : in std_logic;
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red,
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orange,
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green : out std_logic
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);
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end entity traffic_light;
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architecture V1 of traffic_light is
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component tick1s is
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port (
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rst,
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clk : in std_logic;
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output : out std_logic
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);
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end component;
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begin
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end architecture V1;
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