66 lines
1.7 KiB
VHDL
66 lines
1.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity tick1s is
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port (
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rst,
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clk : in std_logic;
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output : out std_logic
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);
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end entity tick1s;
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architecture V1 of tick1s is
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component count is
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port(
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rst,
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clk : in std_logic;
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input : in std_logic_vector (31 downto 0);
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output : out std_logic_vector (31 downto 0)
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);
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end component;
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component tick1ms is
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port (
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rst,
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clk : in std_logic;
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output : out std_logic
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);
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end component;
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signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
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signal counter_out : std_logic_vector (31 downto 0);
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signal ms_clk : std_logic;
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begin
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G1: entity work.tick1ms(V1)
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port map(
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rst => rst,
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clk => clk,
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output => ms_clk
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);
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G2: entity work.count(V1)
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port map(
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rst => rst,
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-- on utilise le signal de sortie du tick1ms comme clock pour notre counter.
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clk => ms_clk,
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in_s => counter_in,
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out_s => counter_out
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);
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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output <= '0';
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--elsif counter_out = x"000003e8" then (Valeur pour une vraie seconde)
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elsif counter_out = x"0000000A" then -- Valeur utilisee pour tester sans simuler un nombre trop consequent de tour d'horloges
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output <= '1';
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counter_in <= (others => '0');
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else
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output <= '0';
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if ms_clk = '1' then
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counter_in <= counter_out;
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end if;
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end if;
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end if;
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end process;
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end architecture V1;
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