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tick1ms.vhdl

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+library ieee;
+use ieee.std_logic_1164.all;
+
+-- utilise un counter pour envoyer un signal toutes les milisecondes
+-- la frequence de rafraichissement de notre programme (clock rate) est de 10ns (100MHz)
+-- il faut alors envoyer un signal toutes les 100,000 (x"186A0") tours d'horloge.
+entity tick1ms is
+    port (
+        rst,
+        clk : in std_logic;
+        output : out std_logic
+    );
+end entity tick1ms;
+architecture V1 of tick1ms is
+    component count is
+    port(
+        rst,
+        clk : in std_logic;
+        input : in std_logic_vector (31 downto 0);
+        output : out std_logic_vector (31 downto 0)
+    );
+    end component;
+    -- instanciation du signal in_s a 0.
+    signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
+    signal counter_out : std_logic_vector (31 downto 0);
+begin
+    G1: entity work.count(V1)
+    port map(
+        rst => rst,
+        clk => clk,
+        in_s => counter_in,
+        out_s => counter_out
+    );
+
+    process(clk, rst)
+    begin
+        if rising_edge(clk) then
+            if rst = '1' then
+                output <= '0';
+            elsif counter_out = x"000001f4" then -- 1ms se sont ecoulees
+                output <= '1';
+                counter_in <= (others => '0');
+            else 
+                output <= '0';
+                counter_in <= counter_out;
+            end if;
+        end if;
+    end process;
+
+end architecture V1;