working implementation

tb_traffic_light.vhdl

@@ -15,7 +15,7 @@ architecture sim of tb_traffic_light is
 
     constant clk_period : time := 1000 ns;
 begin
-    -- Instantiate DUT
+    -- instanciation de l'uut
     UUT: entity work.traffic_light
         port map (
             rst    => rst_s,
@@ -25,7 +25,7 @@ begin
             red => red_s
         );
 
-    -- Clock generator
+    -- horloge
     clk_proc: process
     begin
         while true loop
@@ -36,7 +36,7 @@ begin
         end loop;
     end process;
 
-    -- Stimulus
+    -- processus
     stim_proc: process
     begin
         -- apply reset