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working implementation

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This commit is contained in:
Tiago Batista Cardoso
2025-12-26 12:20:48 +01:00
parent c350456d06
commit 6e000cdcaa
3 changed files with 22 additions and 21 deletions
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34
traffic_light.vhdl
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@@ -11,7 +11,6 @@ entity traffic_light is
green : out std_logic
);
end entity traffic_light;
architecture V1 of traffic_light is
component count is
port(
@@ -28,11 +27,11 @@ architecture V1 of traffic_light is
output : out std_logic
);
end component;
signal s_clk : std_logic;
signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
signal counter_out : std_logic_vector (31 downto 0);
signal s_clk : std_logic;
begin
G1: entity work.tick1ms(V1)
G1: entity work.tick1s(V1)
port map(
rst => rst,
clk => clk,
@@ -54,27 +53,28 @@ begin
green <= '1';
orange <= '0';
red <= '0';
s_clk <= '0';
counter_in <= x"00000000";
else
if counter_out < x"0000000a" then
-- 10 seconds green light
if counter_out < x"0000000a" then
green <= '1';
orange <= '0';
red <= '0';
if s_clk = '1' then
counter_in <= counter_out;
end if;
elsif counter_out < x"00000014" then
-- 2 seconds orange light
elsif counter_out < x"0000000c" then
green <= '0';
orange <= '1';
red <= '0';
if s_clk = '1' then
counter_in <= counter_out;
end if;
else
if s_clk = '1' then
counter_in <= counter_out;
end if;
-- 10 seconds red light
elsif counter_out < x"00000016" then
green <= '0';
orange <= '0';
red <= '1';
-- reset
else
counter_in <= (others => '0');
end if;
if s_clk = '1' then
counter_in <= counter_out;
end if;
end if;
end if;