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working implementation

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This commit is contained in:
Tiago Batista Cardoso
2025-12-26 12:20:48 +01:00
parent c350456d06
commit 6e000cdcaa
3 changed files with 22 additions and 21 deletions
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6
tb_traffic_light.vhdl
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@@ -15,7 +15,7 @@ architecture sim of tb_traffic_light is
constant clk_period : time := 1000 ns; constant clk_period : time := 1000 ns;
begin begin
-- Instantiate DUT -- instanciation de l'uut
UUT: entity work.traffic_light UUT: entity work.traffic_light
port map ( port map (
rst => rst_s, rst => rst_s,
@@ -25,7 +25,7 @@ begin
red => red_s red => red_s
); );
-- Clock generator -- horloge
clk_proc: process clk_proc: process
begin begin
while true loop while true loop
@@ -36,7 +36,7 @@ begin
end loop; end loop;
end process; end process;
-- Stimulus -- processus
stim_proc: process stim_proc: process
begin begin
-- apply reset -- apply reset

3
tick1s.vhdl
View File

@@ -48,7 +48,8 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
output <= '0'; output <= '0';
elsif counter_out = x"000003e8" then --elsif counter_out = x"000003e8" then (Valeur pour une vraie seconde)
elsif counter_out = x"0000000A" then -- Valeur utilisee pour tester sans simuler un nombre trop consequent de tour d'horloges
output <= '1'; output <= '1';
counter_in <= (others => '0'); counter_in <= (others => '0');
else else

26
traffic_light.vhdl
View File

@@ -11,7 +11,6 @@ entity traffic_light is
green : out std_logic green : out std_logic
); );
end entity traffic_light; end entity traffic_light;
architecture V1 of traffic_light is architecture V1 of traffic_light is
component count is component count is
port( port(
@@ -28,11 +27,11 @@ architecture V1 of traffic_light is
output : out std_logic output : out std_logic
); );
end component; end component;
signal s_clk : std_logic;
signal counter_in : std_logic_vector (31 downto 0) := (others => '0'); signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
signal counter_out : std_logic_vector (31 downto 0); signal counter_out : std_logic_vector (31 downto 0);
signal s_clk : std_logic;
begin begin
G1: entity work.tick1ms(V1) G1: entity work.tick1s(V1)
port map( port map(
rst => rst, rst => rst,
clk => clk, clk => clk,
@@ -54,30 +53,31 @@ begin
green <= '1'; green <= '1';
orange <= '0'; orange <= '0';
red <= '0'; red <= '0';
s_clk <= '0';
counter_in <= x"00000000";
else else
-- 10 seconds green light
if counter_out < x"0000000a" then if counter_out < x"0000000a" then
green <= '1'; green <= '1';
orange <= '0'; orange <= '0';
red <= '0'; red <= '0';
if s_clk = '1' then -- 2 seconds orange light
counter_in <= counter_out; elsif counter_out < x"0000000c" then
end if;
elsif counter_out < x"00000014" then
green <= '0'; green <= '0';
orange <= '1'; orange <= '1';
red <= '0'; red <= '0';
if s_clk = '1' then -- 10 seconds red light
counter_in <= counter_out; elsif counter_out < x"00000016" then
end if; green <= '0';
orange <= '0';
red <= '1';
-- reset
else else
counter_in <= (others => '0');
end if;
if s_clk = '1' then if s_clk = '1' then
counter_in <= counter_out; counter_in <= counter_out;
end if; end if;
end if; end if;
end if; end if;
end if;
end process; end process;
end architecture V1; end architecture V1;