51 lines
1.1 KiB
VHDL
51 lines
1.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity tb_traffic_light is
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end entity;
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architecture sim of tb_traffic_light is
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signal rst_s : std_logic := '1';
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signal clk_s : std_logic := '0';
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signal out_s : std_logic;
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constant clk_period : time := 1000 ns;
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begin
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-- Instantiate DUT
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UUT: entity work.tick1s
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port map (
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rst => rst_s,
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clk => clk_s,
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output => out_s
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);
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-- Clock generator
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clk_proc: process
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begin
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while true loop
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clk_s <= '0';
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wait for clk_period/2;
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clk_s <= '1';
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wait for clk_period/2;
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end loop;
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end process;
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-- Stimulus
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stim_proc: process
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begin
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-- apply reset
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rst_s <= '1';
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wait for 2500 ns;
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rst_s <= '0';
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wait for clk_period;
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wait for clk_period;
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while true loop
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wait until rising_edge(clk_s);
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end loop;
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end process stim_proc;
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end architecture sim;
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