33 lines
879 B
VHDL
33 lines
879 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity count is
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port (
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rst,
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clk : in std_logic;
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in_s: in std_logic_vector (31 downto 0);
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out_s : out std_logic_vector (31 downto 0)
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);
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end entity count;
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architecture V1 of count is
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begin
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-- l'utilisation d'entiers 32 bits nous limite a une valeur maximale de 2,147,483,647.
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-- dans le cas d'un overflow, la valeur se reinitialise a 0.
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assert in_s /= x"FFFFFFFF" report "counter overflow. wrapping value to 0" severity WARNING;
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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out_s <= (others => '0');
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else
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out_s <= to_std_logic_vector(unsigned(in_s) + 1);
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end if;
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end if;
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end process;
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end architecture V1;
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