first

count.vhdl

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity count is
+    port (
+        rst,
+        clk : in std_logic;
+        in_s: in std_logic_vector (31 downto 0);
+        out_s : out std_logic_vector (31 downto 0)
+    );
+end entity count;
+
+architecture V1 of count is
+begin
+    -- l'utilisation d'entiers 32 bits nous limite a une valeur maximale de 2,147,483,647.
+    -- dans le cas d'un overflow, la valeur se reinitialise a 0.
+    assert in_s /= x"FFFFFFFF" report "counter overflow. wrapping value to 0" severity WARNING;
+
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            if rst = '1' then
+                out_s <= (others => '0'); 
+            else
+                out_s <= to_std_logic_vector(unsigned(in_s) + 1);
+            end if;
+        end if;
+    end process;
+
+end architecture V1;

tb_traffic_light.vhdl

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity tb_traffic_light is
+end entity;
+
+architecture sim of tb_traffic_light is
+    signal rst_s   : std_logic := '1';
+    signal clk_s   : std_logic := '0';
+    signal out_s   : std_logic;
+
+    constant clk_period : time := 1000 ns;
+begin
+    -- Instantiate DUT
+    UUT: entity work.tick1s
+        port map (
+            rst    => rst_s,
+            clk    => clk_s,
+            output => out_s
+        );
+
+    -- Clock generator
+    clk_proc: process
+    begin
+        while true loop
+            clk_s <= '0';
+            wait for clk_period/2;
+            clk_s <= '1';
+            wait for clk_period/2;
+        end loop;
+    end process;
+
+    -- Stimulus
+    stim_proc: process
+    begin
+        -- apply reset
+        rst_s <= '1';
+        wait for 2500 ns;
+        rst_s <= '0';
+        wait for clk_period;
+
+        wait for clk_period;
+
+        while true loop
+            wait until rising_edge(clk_s);
+        end loop;
+    end process stim_proc;
+end architecture sim;

tick1ms.vhdl

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+library ieee;
+use ieee.std_logic_1164.all;
+
+-- utilise un counter pour envoyer un signal toutes les milisecondes
+-- la frequence de rafraichissement de notre programme (clock rate) est de 10ns (100MHz)
+-- il faut alors envoyer un signal toutes les 100,000 (x"186A0") tours d'horloge.
+entity tick1ms is
+    port (
+        rst,
+        clk : in std_logic;
+        output : out std_logic
+    );
+end entity tick1ms;
+architecture V1 of tick1ms is
+    component count is
+    port(
+        rst,
+        clk : in std_logic;
+        input : in std_logic_vector (31 downto 0);
+        output : out std_logic_vector (31 downto 0)
+    );
+    end component;
+    -- instanciation du signal in_s a 0.
+    signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
+    signal counter_out : std_logic_vector (31 downto 0);
+begin
+    G1: entity work.count(V1)
+    port map(
+        rst => rst,
+        clk => clk,
+        in_s => counter_in,
+        out_s => counter_out
+    );
+
+    process(clk, rst)
+    begin
+        if rising_edge(clk) then
+            if rst = '1' then
+                output <= '0';
+            elsif counter_out = x"000001f4" then -- 1ms se sont ecoulees
+                output <= '1';
+                counter_in <= (others => '0');
+            else 
+                output <= '0';
+                counter_in <= counter_out;
+            end if;
+        end if;
+    end process;
+
+end architecture V1;

tick1s.vhdl

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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tick1s is
+    port (
+        rst,
+        clk : in std_logic;
+        output : out std_logic
+    );
+end entity tick1s;
+architecture V1 of tick1s is
+    component count is
+    port(
+        rst,
+        clk : in std_logic;
+        input : in std_logic_vector (31 downto 0);
+        output : out std_logic_vector (31 downto 0)
+    );
+    end component;
+    component tick1ms is
+    port (
+        rst,
+        clk : in std_logic;
+        output : out std_logic
+    );
+    end component;
+    signal counter_in : std_logic_vector (31 downto 0) := (others => '0');
+    signal counter_out : std_logic_vector (31 downto 0);
+    signal ms_s : std_logic;
+begin
+    G1: entity work.tick1ms(V1)
+    port map(
+        rst => rst,
+        clk => clk,
+        output => ms_s
+    );
+    G2: entity work.count(V1)
+    port map(
+        rst => rst,
+        clk => ms_s,
+        in_s => counter_in,
+        out_s => counter_out
+    );
+
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            if rst = '1' then
+                output <= '0';
+            elsif counter_out = x"000003e8" then
+                output <= '1';
+                counter_in <= (others => '0');
+            else
+                output <= '0';
+                if ms_s = '1' then
+                    counter_in <= counter_out;
+                end if;
+            end if;
+
+               -- if output = '1' then
+               -- else
+               --     if ms_s = '1' then
+               --         counter_in <= counter_out;
+               --     end if;
+               -- end if;
+        end if;
+    end process;
+    
+    
+end architecture V1;

traffic_light.vhdl

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+library ieee;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_1164.all;
+
+entity traffic_light is
+    port (
+        rst,
+        clk : in std_logic;
+        red,
+        orange,
+        green : out std_logic
+    );
+end entity traffic_light;
+
+architecture V1 of traffic_light is
+    component tick1s is 
+    port (
+        rst,
+        clk : in std_logic;
+        output : out std_logic
+    );
+    end component;
+begin
+    
+    
+end architecture V1;